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Microchip Technology /ATSAMV70J19B /ISI /CFG1

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Interpret as CFG1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HSYNC_POL)HSYNC_POL 0 (VSYNC_POL)VSYNC_POL 0 (PIXCLK_POL)PIXCLK_POL 0 (GRAYLE)GRAYLE 0 (EMB_SYNC)EMB_SYNC 0 (CRC_SYNC)CRC_SYNC 0FRATE0 (DISCR)DISCR 0 (FULL)FULL 0 (BEATS_4)THMASK 0SLD0SFD

THMASK=BEATS_4

Description

ISI Configuration 1 Register

Fields

HSYNC_POL

Horizontal Synchronization Polarity
VSYNC_POL

Vertical Synchronization Polarity
PIXCLK_POL

Pixel Clock Polarity
GRAYLE

Grayscale Little Endian
EMB_SYNC

Embedded Synchronization
CRC_SYNC

Embedded Synchronization Correction
FRATE

Frame Rate [0…7]
DISCR

Disable Codec Request
FULL

Full Mode is Allowed
THMASK

Threshold Mask

0 (BEATS_4): Only 4 beats AHB burst allowed

1 (BEATS_8): Only 4 and 8 beats AHB burst allowed

2 (BEATS_16): 4, 8 and 16 beats AHB burst allowed
SLD

Start of Line Delay
SFD

Start of Frame Delay

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data